Hardware-software co-design of an iris recognition algorithm

This paper describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32- bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared to a conventional software-based application. Experimental results show that with a clock speed of 40 MHz, an IrisCode is obtained in less than 523 ms from an image of 640x480 pixels, which is just 20% of the total time needed by a software solution running on the same microprocessor embedded in the architecture.Peer ReviewedPreprin

Acceleration of Complex Algorithms on a Fast Reconfigurable Embedded System on Spartan-3

Complex algorithms usually require several computation stages. Many embedded microprocessors have not enough computational performance to resolve these algorithms in a reasonable time, so dedicated coprocessors accelerate them although the main drawback is the area devoted to them. A reconfigurable coprocessor can drastically reduce the area, since it accommodates a set of coprocessors whose execution is multiplexed on time, although the reconfiguration speed reduces the overall system performance. Although self-reconfigurable systems are possible on Spartan-3 FPGAs, it requires a hard design task due to the lack of software and hardware support available on higher-cost families. This paper describes the architecture of a fast self-reconfigurable embedded system mapped on Spartan-3, used as computation platform to solve a complex algorithm, such as the image-processing carried out in a fingerprint biometric algorithm. In order to reduce the reconfiguration time, the system uses our custom-made memory and reconfiguration controllers. Moreover, the dynamic coprocessor can access directly to external memory through our memory controller to improve processing time.Peer ReviewedPostprint (published version

Unidad aritmética en coma flotante para sistemas autoreconfigurables dinámicamente sobre Spartan-3 basados en Microblaze

El presente artículo muestra la implementación de una unidad en coma flotante (FPU) que actúa como coprocesador dentro de un sistema auto-reconfigurable dinámicamente. La FPU tiene capacidad para resolver operaciones básicas como la suma, la resta, el producto, el cociente, la raíz cuadrada, la inversa y el cuadrado. Además, dispone de un registro en el que se almacena el último resultado obtenido con la intención de utilizarlo como operador en el siguiente cálculo, de modo que se reducen los accesos a los buses de comunicación en la resolución de las operaciones matemáticas. El diseño emplea Microblaze como microprocesador del sistema y su implementación se ha realizado sobre una FPGA Spartan 3 de bajo coste. El artículo muestra resultados experimentales en relación al área total ocupada, así como los tiempos de ejecución obtenidos con un ejemplo particular basado en un algoritmo de CORDIC resuelto en coma flotante.Peer ReviewedPostprint (author’s final draft

Implementación mediante FPGA de un sistema SVM de verificación de locutor

Los sistemas biométricos caracterizados por su alto nivel de seguridad se implementan habitualmente con sistemas procesadores de altas prestaciones como los ordenadores personales. Estos procesadores trabajan en un rango de frecuencias de GHz que les permiten realizar millones de operaciones por segundo, de forma que pueden ejecutar en tiempo real complejos algoritmos de verificación. Sin embargo, esta solución de implementación tiene el inconveniente del elevado coste. La utilización de dispositivos programables del tipo FPGA (Field Programmable Gate Array) permite obtener a bajo coste soluciones a medida con las que se consiguen elevadas velocidades de proceso similares a los sistemas μP de altas prestaciones. En este artículo se presenta el diseño e implementación sobre una FPGA de un sistema de verificación de locutor basado en los coeficientes Mel-Cepstrum y en un algoritmo de clasificación SVM (Support Vector Machines). Los resultados experimentales obtenidos con el diseño propuesto muestran una velocidad de proceso equiparable a la conseguida con un ordenador personal basado en el μP Pentium IV.Peer ReviewedPostprint (published version

Effectiveness of an intervention for improving drug prescription in primary care patients with multimorbidity and polypharmacy:Study protocol of a cluster randomized clinical trial (Multi-PAP project)

This study was funded by the Fondo de Investigaciones Sanitarias ISCIII (Grant Numbers PI15/00276, PI15/00572, PI15/00996), REDISSEC (Project Numbers RD12/0001/0012, RD16/0001/0005), and the European Regional Development Fund ("A way to build Europe").Background: Multimorbidity is associated with negative effects both on people's health and on healthcare systems. A key problem linked to multimorbidity is polypharmacy, which in turn is associated with increased risk of partly preventable adverse effects, including mortality. The Ariadne principles describe a model of care based on a thorough assessment of diseases, treatments (and potential interactions), clinical status, context and preferences of patients with multimorbidity, with the aim of prioritizing and sharing realistic treatment goals that guide an individualized management. The aim of this study is to evaluate the effectiveness of a complex intervention that implements the Ariadne principles in a population of young-old patients with multimorbidity and polypharmacy. The intervention seeks to improve the appropriateness of prescribing in primary care (PC), as measured by the medication appropriateness index (MAI) score at 6 and 12months, as compared with usual care. Methods/Design: Design:pragmatic cluster randomized clinical trial. Unit of randomization: family physician (FP). Unit of analysis: patient. Scope: PC health centres in three autonomous communities: Aragon, Madrid, and Andalusia (Spain). Population: patients aged 65-74years with multimorbidity (≥3 chronic diseases) and polypharmacy (≥5 drugs prescribed in ≥3months). Sample size: n=400 (200 per study arm). Intervention: complex intervention based on the implementation of the Ariadne principles with two components: (1) FP training and (2) FP-patient interview. Outcomes: MAI score, health services use, quality of life (Euroqol 5D-5L), pharmacotherapy and adherence to treatment (Morisky-Green, Haynes-Sackett), and clinical and socio-demographic variables. Statistical analysis: primary outcome is the difference in MAI score between T0 and T1 and corresponding 95% confidence interval. Adjustment for confounding factors will be performed by multilevel analysis. All analyses will be carried out in accordance with the intention-to-treat principle. Discussion: It is essential to provide evidence concerning interventions on PC patients with polypharmacy and multimorbidity, conducted in the context of routine clinical practice, and involving young-old patients with significant potential for preventing negative health outcomes. Trial registration: Clinicaltrials.gov, NCT02866799Publisher PDFPeer reviewe

Hardware-software co-design of an iris recognition algorithm

This paper describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32- bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared to a conventional software-based application. Experimental results show that with a clock speed of 40 MHz, an IrisCode is obtained in less than 523 ms from an image of 640x480 pixels, which is just 20% of the total time needed by a software solution running on the same microprocessor embedded in the architecture.Peer Reviewe

A proposal for a spherical option in WIMS

SIGLELD:9091.9F(AEEW-M--1846). / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Ataques por canal lateral sobre el algoritmo de encriptación AES implementado en MicroBlaze.

Este artículo presenta un procedimiento simple para la obtención de la clave criptográfica del algoritmo AES ejecutado sobre MicroBlaze. La clave se obtiene analizando la correlación estadística que existe entre ésta y el consumo del dispositivo hardware que ejecuta el propio algoritmo. El trabajo también muestra como las contramedidas clásicas de enmascarado del texto plano son únicamente eficientes frente ataques de primer orden. Los resultados experimentales muestran diferentes ataques realizados sobre varios bloques del algoritmo, y concluyen que es posible obtener la clave criptográfica tomando un número de trazas de corriente inferior a 40.Postprint (published version

Ataques por canal lateral sobre el algoritmo de encriptación AES implementado en MicroBlaze.

Este artículo presenta un procedimiento simple para la obtención de la clave criptográfica del algoritmo AES ejecutado sobre MicroBlaze. La clave se obtiene analizando la correlación estadística que existe entre ésta y el consumo del dispositivo hardware que ejecuta el propio algoritmo. El trabajo también muestra como las contramedidas clásicas de enmascarado del texto plano son únicamente eficientes frente ataques de primer orden. Los resultados experimentales muestran diferentes ataques realizados sobre varios bloques del algoritmo, y concluyen que es posible obtener la clave criptográfica tomando un número de trazas de corriente inferior a 40

Implementation on MicroBlaze of AES algorithm to reveal fake keys against side-channel attacks

This paper presents a new proposal for hiding the cryptographic key, when the so-called side-channel attacks (SCAs) are applied to break the security of AES-128. The algorithm was executed on MicroBlaze, but the proposed method is generic and can be extended to any other microprocessor. SCAs are based on examining the correlation produced between the data and operations performed by the microprocessor and its actual power consumption. Traditionally, such weakness is counteracted by introducing countermeasures addressed to reduce as much as possible this correlation, making data and power consumption independent. On the contrary, the proposal presented in this paper introduces some modifications in the AES algorithm. These changes aim at concealing the true key by reinforcing the correlation coefficient in such a way that a classical attack leads to a false key. This way, the system misleads the attacker and apparently behaves as an unprotected system that, in fact, reveals a false positive. The complete system was built on a Virtex-5 FPGA. Experimental results show the strength of our implementation, which is capable of successfully hiding the true cryptographic key